View HYB3118165BST-50_2741540.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

semiconductor group 1 1998-10-01 ? 1 048 576 words by 16-bit organization ? 0 to 70 c operating temperature ? hyper page mode-edo-operation ? performance: ? power dissipation, refresh & addressing: ? read, write, read-modify-write, cas-before- ras refresh, ras-only refresh and hidden refresh ? all inputs, outputs and clocks fully ttl (5 v versions) and lv-ttl (3.3 v version)-compatible ? plastic package: p-soj-42-1 400 mil p-tsopii-50/44-1 400 mil -50 -60 t rac ras access time 50 60 ns t cac cas access time 13 15 ns t aa access time from address 25 30 ns t rc read/write cycle time 84 104 ns t hpc hyper page mode (edo) cycle time 20 25 ns hyb5118165 hyb3118165 -50 -60 -50 -60 power supply 5 v 10 % 3.3 v 0.3 v addressing 10/10 10/10 refresh 1024 cycles / 16 ms active 715 632 468 414 mw ttl standby 11 7.2 mw cmos standby 5.5 3.6 mw 1m 16-bit dynamic ram 1k refresh (hyper page mode-edo) advanced information hyb 5118165bsj/bst-50/-60 hyb 3118165bsj/bst-50/-60
hyb 5118165bsj/bst-50/-60 hyb 3118165bsj/bst-50/-60 1m 16 edo-dram semiconductor group 2 1998-10-01 the hyb 5(3)118165 are 16 mbit dynamic rams based on die revisions g & f and organized as 1 048 576 words by 16-bits. the hyb 5(3)118165 utilizes a submicron cmos silicon gate process technology, as well as advanced circuit techniques to provide wide operating margins, both internally and for the system user. multiplexed address inputs permit the hyb 5(3)18165 to be packaged in a standard soj-42 and tsopii-50/44 plastic package with 400 mil width. these packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment. ordering information type ordering code package descriptions hyb 5118165bsj-50 q67100-q1107 p-soj-42-1 400 mil 5 v 50 ns edo-dram hyb 5118165bsj-60 q67100-q1108 p-soj-42-1 400 mil 5 v 60 ns edo-dram hyb 3118165bsj-50 on request p-soj-42-1 400 mil 3.3 v 50 ns edo-dram hyb 3118165bsj-60 on request p-soj-42-1 400 mil 3.3 v 60 ns edo-dram hyb 5118165bst-50 on request p-tsopii-50/44-1 400 mil 5 v 50 ns edo-dram hyb 5118165bst-60 on request p-tsopii-50/44-1 400 mil 5 v 60 ns edo-dram hyb 3118165bst-50 on request p-tsopii-50/44-1 400 mil 3.3 v 50 ns edo-dram hyb 3118165bst-60 on request p-tsopii-50/44-1 400 mil 3.3 v 60 ns edo-dram
hyb 5118165bsj/bst-50/-60 hyb 3118165bsj/bst-50/-60 1m 16 edo-dram semiconductor group 3 1998-10-01 pin names and configuration hyb 5(3)118165 row address inputs a0 - a9 column address inputs a0 - a9 row address strobe ras upper column address strobe ucas lower column address strobe lcas output enable oe data input/output i/o1 - i/o16 read/write input we power supply v cc ground (0 v) v ss not connected n.c. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 a5 a6 a7 oe a8 ucas a9 i/o11 i/o13 i/o12 a0 a1 a2 i/o3 i/o4 i/o5 i/o6 i/o7 we ras n.c. n.c. spp02812 v ss ss v cc v i/o8 i/o10 i/o16 i/o15 ss v i/o1 i/o2 v cc 21 19 20 18 22 v cc n.c. n.c. a3 a4 lcas n.c. 42 41 40 i/o9 i/o14 p-soj-42-1 (400 mil) spp03457 20 28 19 17 18 16 15 i/o1 i/o2 i/o4 n.c. cc v 9 10 11 2 3 4 5 1 40 32 31 30 29 36 35 34 7 6 8 33 i/o7 i/o6 i/o16 we a6 a5 a4 a3 a2 a0 22 21 ucas a1 23 24 25 ss v 46 47 48 50 49 42 43 44 45 41 lcas n.c. a7 a8 a9 oe n.c. ras a11 / n.c. a10 / n.c. 26 27 ss v v cc i/o3 cc v i/o5 i/o8 v ss i/o15 i/o14 i/o13 i/o12 i/o11 i/o10 i/o9 n.c. n.c. p-tsopii-50/44-1 (400 mil)
hyb 5118165bsj/bst-50/-60 hyb 3118165bsj/bst-50/-60 1m 16 edo-dram semiconductor group 4 1998-10-01 block diagram for hyb 5118165bsj data in buffer data out buffer i/o1 i/o2 i/o16 oe column decoder sense amplifier i/o gating & no.2 clock generator column address buffers (10) refresh controller refresh counter (10) buffers (10) address row no.1 clock generator 10 10 memory array decoder row . . . . . . . . . . . . 16 16 16 10 10 we lcas ras spb02826 ... 10 ... . ucas generator voltage down v cc cc v (internal) 1024 x 1024 x 16 1024 1024 16 x a9 a8 a7 a6 a5 a4 a3 a2 a1 a0
hyb 5118165bsj/bst-50/-60 hyb 3118165bsj/bst-50/-60 1m 16 edo-dram semiconductor group 5 1998-10-01 absolute maximum ratings operating temperature range ........................................................................................... 0 to 70 c storage temperature range........................................................................................ C 55 to 150 c input/output voltage (5 v versions) .................................................... C 0.5 to min ( v cc + 0.5, 7.0) v input/output voltage (3.3 v versions) ................................................. C 0.5 to min ( v cc + 0.5, 4.6) v power supply voltage (5 v versions) ....................................................................... C 1.0 v to 7.0 v power supply voltage (3.3 v versions) .................................................................... C 1.0 v to 4.6 v power dissipation (5 v versions) ............................................................................................. 1. 0w power dissipation (3.3 v versions) .......................................................................................... 0.5 w data out current (short circuit) ............................................................................................... .50ma note: stresses above those listed under absolute maximum ratings may cause permanent damage of the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. dc characteristics t a = 0 to 70 c, v ss = 0 v, t t = 2 ns parameter symbol limit values unit test condition min. max. 5 v versions power supply voltage v cc 4.5 5.5 v input high voltage v ih 2.4 v cc + 0.5 v 1 input low voltage v il C 0.5 0.8 v 1 output high voltage ( i out = C 5 ma) v oh 2.4 C v 1 output low voltage ( i out = 4.2 ma) v ol C 0.4 v 1 3.3 v versions power supply voltage v cc 3.0 3.6 v input high voltage v ih 2.0 v cc + 0.5 v 1 input low voltage v il C 0.5 0.8 v 1 ttl output high voltage ( i out = C 2 ma) v oh 2.4 C v 1 ttl output low voltage ( i out = 2 ma) v ol C 0.4 v 1 cmos output high voltage ( i out = C 100 m a) v oh v cc C 0.2 C v cmos output low voltage ( i out = 100 m a) v ol C 0.2 v
hyb 5118165bsj/bst-50/-60 hyb 3118165bsj/bst-50/-60 1m 16 edo-dram semiconductor group 6 1998-10-01 dc characteristics (contd) t a = 0 to 70 c, v ss = 0 v, t t = 2 ns parameter symbol limit values unit notes min. max. common parameters input leakage current (0 v v ih v cc + 0.3 v, all other pins = 0 v) i i(l) C 10 10 m a 1 output leakage current (do is disabled, 0 v v out v cc + 0.3 v) i o(l) C 10 10 m a 1 average v cc supply current -50 ns version -60 ns version ( ras, cas, address cycling: t rc = t rc min. ) i cc1 C C 130 115 ma ma 2, 3, 4 2, 3, 4 standby v cc supply current ( ras = cas = v ih ) i cc2 C 2 ma C average v cc supply current, during ras-only refresh cycles -50 ns version -60 ns version ( ras cycling, cas = v ih , t rc = t rc min. ) i cc3 C C 130 115 ma ma 2, 4 2, 4 average v cc supply current, during hyper page mode (edo) -50 ns version -60 ns version ( ras = v il , cas, address cycling: t pc = t pc min. ) i cc4 C C 50 40 ma ma 2, 3, 4 2, 3, 4 standby v cc supply current ( ras = cas = v cc C 0.2 v) i cc5 C1ma 1 average v cc supply current, during cas-before- ras refresh mode -50 ns version -60 ns version ( ras, cas cycling: t rc = t rc min. ) i cc6 C C 130 115 ma ma 2, 4 2, 4
hyb 5118165bsj/bst-50/-60 hyb 3118165bsj/bst-50/-60 1m 16 edo-dram semiconductor group 7 1998-10-01 capacitance t a = 0 to 70 c, f = 1 mhz parameter symbol limit values unit min. max. input capacitance (a0 to a11) c i1 C5pf input capacitance ( ras, ucas, lcas, we, oe) c i2 C7pf i/o capacitance (i/o1 - i/o16) c io C7pf ac characteristics 5, 6 t a = 0 to 70 c, v cc = 5 v 10 % / v cc = 3.3 v 0.3 v, t t = 2 ns parameter symbol limit values unit note -50 -60 min. max. min. max. common parameters random read or write cycle time t rc 84 C 104 C ns ras precharge time t rp 30 C 40 C ns ras pulse width t ras 50 10k 60 10k ns cas pulse width t cas 8 10k 10 10k ns row address setup time t asr 0C0Cns row address hold time t rah 8 C 10 C ns column address setup time t asc 0C0Cns column address hold time t cah 8 C 10 C ns ras to cas delay time t rcd 12 37 14 45 ns ras to column address delay t rad 10 25 12 30 ns ras hold time t rsh 13 C 15 C ns cas hold time t csh 40 C 50 C ns cas to ras precharge time t crp 5C5Cns transition time (rise and fall) t t 1 50 1 50 ns 7 refresh period for 1k-refresh version t ref C 16 C 16 ms read cycle access time from ras t rac C 50 C 60 ns 8, 9 access time from cas t cac C 13 C 15 ns 8, 9 access time from column address t aa C 25 C 30 ns 8, 10 oe access time t oea C 13 C 15 ns
hyb 5118165bsj/bst-50/-60 hyb 3118165bsj/bst-50/-60 1m 16 edo-dram semiconductor group 8 1998-10-01 column address to ras lead time t ral 25 C 30 C ns read command setup time t rcs 0C0Cns read command hold time t rch 0C0Cns 11 read command hold time referenced to ras t rrh 0C0Cns 11 cas to output in low-z t clz 0C0Cns 8 output buffer turn-off delay t off 0 13 0 15 ns 12 output turn-off delay from oe t oez 0 13 0 15 ns 12 data to cas low delay t dzc 0C0Cns 13 data to oe low delay t dzo 0C0Cns 13 cas high to data delay t cdd 10 C 13 C ns 14 oe high to data delay t odd 10 C 13 C ns 14 write cycle write command hold time t wch 8 C 10 C ns write command pulse width t wp 8 C 10 C ns write command setup time t wcs 0C0Cns 15 write command to ras lead time t rwl 8 C 10 C ns write command to cas lead time t cwl 8 C 10 C ns data setup time t ds 0C0Cns 16 data hold time t dh 8 C 10 C ns 16 read-modify-write cycle read-write cycle time t rwc 113 C 138 C ns ras to we delay time t rwd 64 C 77 C ns 15 cas to we delay time t cwd 27 C 32 C ns 15 column address to we delay time t awd 39 C 47 C ns 15 oe command hold time t oeh 10 C 13 C ns hyper page mode (edo) cycle hyper page mode (edo) cycle time t hpc 20 C 25 C ns cas precharge time t cp 8 C 10 C ns ac characteristics (contd) 5, 6 t a = 0 to 70 c, v cc = 5 v 10 % / v cc = 3.3 v 0.3 v, t t = 2 ns parameter symbol limit values unit note -50 -60 min. max. min. max.
hyb 5118165bsj/bst-50/-60 hyb 3118165bsj/bst-50/-60 1m 16 edo-dram semiconductor group 9 1998-10-01 access time from cas precharge t cpa C 27 C 32 ns 7 output data hold time t coh 5C5Cns ras pulse width in edo mode t ras 50 200k 60 200k ns cas precharge to ras delay t rhcp 27 C 32 C ns oe setup time prior to cas t oes 5C5C5C hyper page mode (edo) read-modify-write cycle hyper page mode (edo) read-write cycle time t prwc 58 C 68 C ns cas precharge to we t cpwd 41 C 49 C ns cas-before- ras refresh cycle cas setup time t csr 10 C 10 C ns cas hold time t chr 10 C 10 C ns ras to cas precharge time t rpc 5C5Cns write to ras precharge time t wrp 10 C 10 C ns write hold time referenced to ras t wrh 10 C 10 C ns cas-before- ras counter test cycle cas precharge time ( cas-before- ras counter test cycle) t cpt 35 C 40 C ns ac characteristics (contd) 5, 6 t a = 0 to 70 c, v cc = 5 v 10 % / v cc = 3.3 v 0.3 v, t t = 2 ns parameter symbol limit values unit note -50 -60 min. max. min. max.
hyb 5118165bsj/bst-50/-60 hyb 3118165bsj/bst-50/-60 1m 16 edo-dram semiconductor group 10 1998-10-01 notes 1. all voltages are referenced to v ss . 2. i cc1 , i cc3 , i cc4 and i cc6 depend on cycle rate. 3. i cc1 and i cc4 depend on output loading. specified values are obtained with the output open. 4. address can be changed once or less while ras = v il . in case of i cc4 it can be changed once or less during a hyper page mode (edo) cycle 5. an initial pause of 200 m s is required after power-up followed by 8 ras cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. in case of using the internal refresh counter, a minimum of 8 cas-before- ras initialization cycles instead of 8 ras cycles are required. 6. ac measurements assume t t = 2 ns. 7. v ih (min.) and v il (max.) are reference levels for measuring timing of input signals. transition times are also measured between v ih and v il . 8. measured with the specified current load and 100 pf at v ol = 0.8 v and v oh = 2.0 v. access time is determined by the latter of t rac , t cac , t aa , t cpa , t oea . t cac is measured from tristate. 9. operation within the t rcd (max.) limit ensures that t rac (max.) can be met. t rcd (max.) is specified as a reference point only. if t rcd is greater than the specified t rcd (max.) limit, then access time is controlled by t cac . 10.operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is specified as a reference point only. if t rad is greater than the specified t rad (max.) limit, then access time is controlled by t aa . 11.either t rch or t rrh must be satisfied for a read cycle. 12. t off (max.) , t oez (max.) define the time at which the output achieves the open-circuit conditions and are not referenced to output voltage levels. t off is referenced from the rising edge of ras or cas, whichever occurs last. 13.either t dzc or t dzo must be satisfied. 14.either t cdd or t odd must be satisfied. 15. t wcs , t rwd , t cwd and t awd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if t wcs > t wcs (min.) , the cycle is an early write cycle and data out pin will remain open-circuit (high impedance) through the entire cycle; if t rwd > t rwd (min.) , t cwd > t cwd (min.) and t awd > t awd (min.) , the cycle is a read-write cycle and i/o will contain data read from the selected cells. if neither of the above sets of conditions is satisfied, the condition of i/o (at access time) is indeterminate. 16.these parameters are referenced to the cas leading edge in early write cycles and to the we leading edge in read-write cycles.
hyb 5118165bsj/bst-50/-60 hyb 3118165bsj/bst-50/-60 1m 16 edo-dram semiconductor group 11 1998-10-01 read cycle spt03043 "h" or "l" oea cac ral t oh ol v (inputs) (outputs) i/o i/o v ih v il v oe we v il v ih v il v ih rac t hi dzo z t clz t t dzc t rcs aa t t lcas v address v il v ih il ucas ras il v ih v v ih t rad asr t row t column rah asc t cah t t rcd t csh t t ras t t odd rrh valid data out oez t t cdd off t hi z t t rsh cas t rc t rch asr t row crp t t rp
hyb 5118165bsj/bst-50/-60 hyb 3118165bsj/bst-50/-60 1m 16 edo-dram semiconductor group 12 1998-10-01 write cycle (early write) spt03044 "h" or "l" rwl ral wcs oh (inputs) (outputs) i/o i/o il v ol v v v ih oe we ih v il v v il v ih t ds t valid dh data in wch t t wp t lcas v address ih v v il il ucas ras v ih ih v v il t rad asr t t rah row t column asc t cwl t cah t t rcd t csh t t ras t z hi t rc cas rsh t asr t row crp t t rp
hyb 5118165bsj/bst-50/-60 hyb 3118165bsj/bst-50/-60 1m 16 edo-dram semiconductor group 13 1998-10-01 write cycle ( oe controlled write) spt03045 "h" or "l" ds ral cas v oh v (inputs) (outputs) i/o i/o v v ol il v ih oe we v il il v ih v ih t dzo hi z t clz t oea t oez t dzc odd t t v address il v v ih lcas ucas ras v il v ih il v ih rad asr t rah t row t t column asc t cah rcd t t t csh t ras t hi valid data t dh oeh t z rwl cwl t t wp t rsh t asr t row crp t t rc t rp
hyb 5118165bsj/bst-50/-60 hyb 3118165bsj/bst-50/-60 1m 16 edo-dram semiconductor group 14 1998-10-01 read-write (read-modify-write) cycle spt03046 "h" or "l" awd oea csh rwd oh i/o (outputs) v ol (inputs) i/o il v v v ih oe we v il v ih v il v ih rac t t dzc t dzo t clz t cac t rcs t aa t v address v il v ih lcas ucas ras ih v il v v il ih rah row asr t t rad t column asc t t t cah t rcd t t t wp data out ds odd oez t t t t data in valid t dh oeh row t cwd t cas t t rsh rwl t t cwl asr t crp t rp t rwc t ras
hyb 5118165bsj/bst-50/-60 hyb 3118165bsj/bst-50/-60 1m 16 edo-dram semiconductor group 15 1998-10-01 hyper page mode (edo) read cycle spt03056 "h" or "l" column 2 data out 1 t t oh ol il ih il ih i/o (output) v v v oe we v v v rcs cac t clz rac t aa t t oes oea t t ih il il ih ih il address v v lcas ucas ras v v v v rcd asc column 1 row asr t rad t t rah t t crp t csh cah t asc t hpc cas t t t cp t rch data out n t data out 2 t coh aa t cpa t cac t t coh t aa cpa t cac t t oez off crp rp rhcp column n cah t cas t t cah asc t t ral rrh t rsh t cas t t t ras t t
hyb 5118165bsj/bst-50/-60 hyb 3118165bsj/bst-50/-60 1m 16 edo-dram semiconductor group 16 1998-10-01 hyper page mode (edo) early write cycle spt03057 "h" or "l" column 2 ds t ih v i/o (input) oe v v il ih v il we v v il ih data in 1 t ds wcs t t dh t wp cwl t t wch t t wcs lcas address v il v ih il v ucas ras v ih il v v ih t column 1 t asc address row asr t rad t rah t t crp t rcd t csh cah asc t hpc cas t t cp t data in n ds data in 2 t dh t cwl wch wp t t t t wcs t dh t t wch wp t cwl crp rp t column n cah t asc t t cas rwl t t cah t ral rsh t cas t rhcp t t ras
hyb 5118165bsj/bst-50/-60 hyb 3118165bsj/bst-50/-60 1m 16 edo-dram semiconductor group 17 1998-10-01 hyper page mode (edo) late write and read-modify-write cycle spt03049 "h" or "l" il data rac (outputs) i/o v oh ol v out data oez t i/o (inputs) oe clz t v il v ih dzc t t cac t ds dzo t odd t v il ih v t awd t aa t oea t t oeh aa ds aa out data t out data oez oez t odd in dh t t t dzc cpa t t in data dh t t t cac t dzc t t cpa oeh clz t wp t t oea t awd t clz t t wp oea t awd t in data ds t dh t odd t wp t oeh t address we lcas ucas v rcs v v ih t row v il ih t cwd t cwl rwd t column il v asr t t rah asc t rad t ih v rcd t t cah cas t ras il v v ih t csh cwd cwl t cwd t column cpwd t t t cpwd column prwc asc t cah t t cp cas t t asc t t cah cwl t rwl t row crp t ral rsh cas t t t asr t ras t t rp
hyb 5118165bsj/bst-50/-60 hyb 3118165bsj/bst-50/-60 1m 16 edo-dram semiconductor group 18 1998-10-01 ras-only refresh cycle spt03050 "h" or "l" oh ol (outputs) address i/o v v v il ih v row lcas ucas ras il v v ih v il ih v rah asr t t ras t row z hi t rc t rpc asr t crp t rp t
hyb 5118165bsj/bst-50/-60 hyb 3118165bsj/bst-50/-60 1m 16 edo-dram semiconductor group 19 1998-10-01 cas-before- ras refresh cycle spt03051 "h" or "l" v il ih ih il ol oh il (outputs) i/o v v (inputs) oe i/o v v v v t off oez t t cdd odd t ih il ih ih il lcas we ucas v v v ras v v wrp csr t t cp t rpc t rp t t wrh t chr hi z ras t rc t t rpc t rp crp t
hyb 5118165bsj/bst-50/-60 hyb 3118165bsj/bst-50/-60 1m 16 edo-dram semiconductor group 20 1998-10-01 hidden refresh cycle (read) spt03053 "h" or "l" v i/o (outputs) ol v (inputs) i/o oh v v il ih v oe we v il ih v il ih v clz rac t t dzo t t dzc t cac oea aa t t address v il ih v lcas ucas ras v il ih v il v ih v column ras t t rah row asr t t rcs asc t t rcd rad t cah t rrh t wrp t t rsh t rc rp t valid data out oez t off t odd t hi z t cdd row wrh t t chr ras t asr t crp t rc t t rp
hyb 5118165bsj/bst-50/-60 hyb 3118165bsj/bst-50/-60 1m 16 edo-dram semiconductor group 21 1998-10-01 hidden refresh cycle (early write) spt03054 "h" or "l" wrp column row address (output) (input) i/o i/o ol v oh v in v v il we il v ih v v il valid data t ds t wcs t dh wp t wch t t asr v lcas ucas ih v t il ih v ras v il ih v ras rad asc rah t t t rcd t t cah t rsh t t rc rp t row hi z t wrh rc t ras chr t t asr t crp t rp t
hyb 5118165bsj/bst-50/-60 hyb 3118165bsj/bst-50/-60 1m 16 edo-dram semiconductor group 22 1998-10-01 cas-before- ras refresh counter test cycle spt03055 "h" or "l" t wch t t dzc t (inputs) (outputs) i/o i/o oh ol v il v v ih v write cycle oe we il il v ih v v ih v (inputs) (outputs) i/o i/o ol v oh v il v ih v t ds z hi data in t wrp wrh t dh t t dzo wcs t t t clz oe we il v ih v il v ih v lcas address ucas ih il v v v il ih v read cycle ras v ih il v wrp t wrh t t rcs aa t cac t asc t t cah column csr t chr t cp t ras t rwl cwl t data out t oez t off t odd oea t rrh ral cas t cdd t rch t t asr row rsh t t rp
hyb 5118165bsj/bst-50/-60 hyb 3118165bsj/bst-50/-60 1m 16 edo-dram semiconductor group 23 1998-10-01 package outlines plastic package p-soj-42-1 (smd) (400mil) (plastic small outline j-leaded) gpj05853 sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm smd = surface mounted device
hyb 5118165bsj/bst-50/-60 hyb 3118165bsj/bst-50/-60 1m 16 edo-dram semiconductor group 24 1998-10-01 gpx05958 20.95 0.13 1) 125 50 26 0.4 +0.05 -0.1 0.1 1 0.1 0.2 11.76 0.1 0.5 50x 0.05 0.05 0.15 -0.03 +0.06 15? 5? 15? 5? 6 max 2.5 max 11 15 10.16 0.13 2) 3) index marking does not include dambar protrusion of 0.13 max per side does not include plastic protrusion of 0.25 max per side does not include plastic or metal protrusion of 0.15 max per side 3) 2) 1) 0.8 19.2 24x 0.8 = 0.2 m 50x 36 40 plastic package p-tsopii-50/44-1 (400 mil) (smd) (plastic thin small outline package (type ii)) sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm smd = surface mounted device

▲Up To Search▲

Price & Availability of HYB3118165BST-50

	To Download HYB3118165BST-50 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .